1. Field of Invention
The present invention relates to wireless network communication device. More particularly, the present invention relates to a fast Walsh transform (FWT) demodulator.
2. Description of Related Art
In transmission media design under the wireless local area network (WLAN) 802.11b, the complementary code keying (CCK) demodulator is one of various key-control modules. The manufacturing cost of this module critically influences the overall cost of the receiving system having the same. Usually, the logic gate-count of a circuit is taken for cost estimation, and the minimum signal-to-noise ratio (SNR) needed by a specific bit error rate is taken for performance estimation of the complementary key-control module.
The FWT demodulator is an ideal one for the complementary key-control module. However, the gate-count in the conventional hardware implementation is rather high. FIG. 1 is a block diagram, schematically illustrating a FWT demodulator used in a usual very large scale integrated (VLSI) circuit. In FIG. 1, it includes a FWT operation circuit 102, a power calculation unit 104, a first-stage comparing unit 106, a second-stage comparing unit 108, a third-stage comparing unit 110, a fourth-stage comparing unit 112, a circulation comparator 114, a differential quadrature phase shift keying (DQPSK) demodulator 116.
The output of the correlator is the 16 outputs of the FWT operation circuit 102. The power calculation unit 104 is composed of 16 power calculation devices (PCD), and the PCD is used to calculate the output power of the FWT operation circuit 102. Therefore, the output of the FWT operation circuit 102 is a complex quantity, which can be expressed as Cout=Cout_RE+j*Cout_IM, wherein Cout is the output of the FWT operation circuit 102, and Cout_RE and Cout_IM respectively represent the real part and the imaginary part of the Cout. The precise power calculation (PWR) can be expressed by Equation (1):PWR=Cout_RE2+Cout_IM2.  (1)Here, Cout_RE is assumed to have WL bits, and therefore each power calculation device (PCD) needs two square operation circuits (or a multiplier) in WL bits, and an adder with 2*WL bits.
The first-stage comparing unit 106 is composed of 8 comparators, the second-stage comparing unit 108 is composed of 4 comparators, the third-stage comparing unit 110 is composed of 2 comparators, and the fourth-stage comparing unit 112 is composed of 1 comparator. The comparing units 106-112 are used to compare the 16 output power values from the correlator (102) one to one, so as to find the maximum power in these 16 power values. In accordance with the foregoing 4 times of calculation and comparing procedures, the circulation comparator 114 further compares the maximum powers obtained from the 4 procedures, to obtain the maximum value. Then, the differential quadrature phase shift keying (DQPSK) demodulator 116 receives the output of maximum power in the correlator 112 that is provided by the circulator 114 and the previous output of the correlator. The outputs of the circulation comparator 114 and the DQPSK demodulator 116 is the operation result of the FWT demodulator 100, which is the output signal CRDM_FWT_ROUT in FIG. 1.
As described above, the power calculation unit is an essential part being used to measure the output power of the FWT demodulator. Since each power calculation unit is composed of 2 square circuits (multiplier) and 1 adder, the FWT demodulator 100 having 16 power calculation units shown in FIG. 1 needs 32 multipliers and 16 adders in total. Since the circuit area of the multiplier is relatively larger (cost is higher), the cost to implement the FWT demodulator in the VLSI circuit is relative high.